Asynchronous DRAMs are externally controlled by a processor using standard RAS (row address sample), CAS (column address sample), WE (write enable) and OE (output enable) signals. Operational speed of such asynchronous DRAMs is determined by the speed internal circuits require to perform operations specified by the control signals. The processor, however, must wait for the asynchronous DRAM to complete the required operation, since changing the control signals of the memory address during operation of the DRAM would interrupt its operation. As a result, the processor must waste valuable time which it could otherwise use to perform other tasks in the system, by being tied up waiting for the memory. The discrepancy in operating frequencies between that of the microprocessor (which presently can be specified to operate at up to e.g. 500 MHz), and the typically maximum operating frequency of asynchronous DRAMs (approximately 60 to 80 MHz) creates a mismatch which is becoming increasingly intolerable for many current applications.
In an attempt to increase the speed of the system, a synchronous interface can be provided to control the DRAM, the interface and DRAM together forming a synchronous DRAM (SDRAM), which is well known in the art. The use of latches for input and output data as well as address and control signals, frees the microprocessor from its waiting state, and allows it to perform other functions while the SDRAM performs its required operation under control of the system clock. In the case of a read operation, for example, after a predetermined number of clock cycles, the microprocessor can access resulting data from the output latches of the SDRAM.
Designers of data path architectures for both DRAMs and SDRAMs have tended to favor use of a bi-directional global data path, using a single global data bus per bit for both read and write operations. The bi-directional global data path has been favored in order to minimize the amount of memory chip area used for conductive data paths.
However, the read and write operations may have different speeds and different requirements on the global data bus. For example, the bus turn-around time between a read operation and a write operation may be too large for the SDRAM cycle time to accommodate. The read operation may be faster than the write operation, or vice versa. In either case, these requirements can be resolved by physically separating the global data bus into distinct read and write global data buses. This resolves bus contention problems, since the two buses operate independently and mutually exclusive of one other. However, this architecture incurs a substantial chip area penalty, due to the requirement to provide a second global data bus structure for the entire die. The penalty becomes increasingly severe for buses which carry wide data word widths.